1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, it is concerned with an improvement of a circuit which carries out equalization of a pair of signal lines by which data is read from a memory cell.
2. Description of the Background Art
FIG. 12 is a diagram showing a read circuit of a conventional semiconductor memory device described, for example, in IEEE Journal of Solid State Circuit, Vol. SC-22, No. 5, pp 733-740. With reference to FIG. 12, an address signal ADD is externally applied to an address pin 1. An address buffer 2 receives address signal ADD applied to address pin 1 and outputs an internal address signal intADD to be applied internally.
An address change detecting circuit 3 receives internal address signal intADD applied from address buffer 2, and outputs an address change signal .phi..sub.1 which attains a H (High) level for a certain period as the internal address signal intADD changes. An inverter 4 receives address change signal .phi..sub.1 applied from address change detecting circuit 3. An inverter 5 has its input node connected to an output node of inverter 4 and outputs an equalize signal .phi..sub.E.
A row decoder 6 receives internal address signal intADD applied from address buffer 2, and raises one of potentials WL.sub.1, WL.sub.2, . . . respectively applied on a plurality of word lines 7a, 7b, . . . from a L (Low) level to the H level in response to the internal address signal intADD. A memory cell array 8 includes a plurality of memory cells 9 (general designation for 9aa, 9ab, . . . ), a plurality of word lines 7 (general designation for 7a, 7b, . . . ), and a plurality of bit line pairs 10 (general designation for 10a, 10b, . . . ) and 11 (general designation for 11a, 11b, . . . ).
In this memory cell array 8, each memory cell 9 is arranged at a crossing of word line 7 and bit line pair 10, 11. Therefore, a plurality of memory cells 9 are arranged in a matrix manner. Also, each of the plurality of memory cells 9 is connected to word line 7 and bit line pair 10, 11.
Each of the plurality of memory cells 9 includes two driver transistors 13 (general designation for 13aa, 13ab, . . . ) and 14 (general designation for 14aa, 14ab, . . . ) formed by n channel MOS transistors, resistors of a high-load type 16 (general designation for 16aa, 16ab, . . . ) and 17 (general designation for 17aa, 17ab, . . . ), and two access transistors 18 (general designation for 18aa, 18ab, . . . ) and 19 (general designation for 19aa, 19ab, . . . ) formed by n channel MOS transistors.
Now, structure of each of the plurality of memory cells 9 will be described. The ground potential is applied to a ground potential node 12. A power supply potential V.sub.CC is applied to a power supply potential node 15. Driver transistors 13 and 14 have their source electrodes connected to ground potential node 12, and have one gate electrode connected to the other drain electrode and the other gate electrode connected to one drain electrode.
Resistor 16 is connected between power supply potential node 15 and the drain electrode of driver transistor 13, and resistor 17 is connected between power supply potential node 15 and the drain electrode of driver transistor 14. Access transistor 18 is connected between bit line 10 and the drain electrode of driver transistor 13 and has its gate electrode connected to word line 7. Access transistor 19 is connected between bit line 11 and the drain electrode of driver transistor 14, and has its gate electrode connected to word line 7.
A column decoder 20 receives internal address signal intADD applied from address buffer 2, and raises one of potentials CSL1, CSL2, . . . respectively applied on a plurality of column selection lines 21 (general designation for 21a, 21b, . . . ) from the L level to the H level in response to the internal address signal intADD.
An I/O gate circuit 22 includes a plurality pairs of two n channel MOS transistors 25 (general designation for 25a, 25b, . . . ) and 26 (general designation for 26a, 26b). In this I/O gate circuit 22, transistors 25 and 26 are respectively connected between bit line pairs 10 and 11 and an I/O line pair 23 and 24. These transistors 25 and 26 have respective gates connected to column selection lines 21. I/O gate circuit 22 transfers a pair of potentials of potentials BL.sub.1 and BL.sub.1 , BL.sub.2 and BL.sub.2 , . . . applied on the plurality of bit line pairs 10, 11 respectively to I/O line pair 23 and 24.
A bit line equalizing circuit 27 receives equalize signal .phi..sub.E from inverter 5 and equalizes the potential on bit line pairs 10 and 11 to a potential V.sub.CC -V.sub.th which is lower than power supply potential V.sub.CC by V.sub.th when the equalize signal .phi..sub.E almost attains the H level of power supply potential V.sub.CC.
This bit line equalizing circuit 27 includes a transistor for precharging 28 (general designation for 28a, 28b, . . . ) which is connected between power supply potential node 15 and bit line 10 and receives equalize signal .phi..sub.E at a gate electrode, a transistor for precharging 29 (general designation for 29a, 29b, . . . ) which is connected between power supply potential node 15 and bit line 11 and receives equalize signal .phi..sub.E at a gate electrode, and a transistor for equalization 30 which is connected between bit lines 10 and 11 and receives equalize signal .phi..sub.E at a gate electrode. Transistors for precharging 28 and 29 have a threshold voltage respectively.
A differential amplifier 31 receives potentials IO, IO applied on I/O line pair 23, 24, and amplifies a potential difference therebetween to output read data RD, RD. An output buffer circuit 32 receives read data RD, RD applied from differential amplifier 31 and outputs output data Dout to an output pin 33.
FIG. 13 is a timing chart showing operations of the semiconductor memory device shown in FIG. 12. Now, operations of the conventional semiconductor device shown in FIG. 12 will be described based on the timing chart shown in FIG. 13. It is assumed that data at the H level and the L level are respectively stored in memory cells 9aa and 9bb of memory cells 9 shown in FIG. 12. Also, it is assumed that the data at the L level is initially read from memory cell 9bb.
In the following description, operations of subsequently reading data at the H level from memory cell 9aa, and then reading data at the L level again from memory cell 9bb will be described.
First, until time t.sub.0 when the externally applied address signal ADD changes from A.sub.2 to A.sub.1 as shown in FIG. 13(a), equalize signal .phi..sub.E output from address change detecting circuit 3 through inverters 4 and 5 is at the L level as shown in FIG. 13(c).
Therefore, precharging transistors 28 and 29 and equalizing transistor 30 receiving equalize signal .phi..sub.E at gates are non-conductive, so that equalization of bit lines is stopped.
At the same time, a potential WL.sub.2 of word line 7b is at the H level as shown in FIG. 13(e). Therefore, access transistors 18bb, 19bb in memory cell 9bb connected to word line 7b are respectively rendered conductive. Accordingly, the L level potential and the H level potential respectively stored in drain electrodes of driver transistors 13bb and 14bb are read to bit lines 10b and 11b, respectively. Thus, potentials BL.sub.2 and BL.sub.2 on bit lines 10b and 11b are at the L level and the H level, respectively, as shown in FIG. 13(i).
At this time, column decoder 20 raises potential CSL.sub.2 on column selection line 21b corresponding to address signal A.sub.2 to the H level as shown in FIG. 13(g). Therefore, in I/O gate circuit 22, n channel MOS transistors 25b and 26b receiving potential CSL.sub.2 at the gate electrodes are respectively rendered conductive.
Therefore, bit lines 10b and 11b are respectively connected to I/O lines 23 and 24 through n channel MOS transistors 25b and 26b. Thus, potentials IO and IO on I/O lines 23 and 24 are at the L level and the H level, respectively as shown in FIG. 13(j).
Differential amplifier 31 receiving potentials IO and IO on I/O lines 23 and 24 outputs read data RD at the L level and read data RD at the H level, as shown in FIG. 13(k). Also, output buffer circuit 32 receiving these outputs supplies output data Dout at the L level to output pin 33, as shown in FIG. 13(m).
Then, as shown in FIG. 13(a) when externally applied address signal ADD changes from A.sub.2 to A.sub.1 at time t.sub.0, correspondingly internal address intADD output from address buffer 2 changes. Accordingly, address change detecting circuit 3 receiving the internal address intADD outputs address change signal .phi..sub.1 which attains the H level for a predetermined period until time t.sub.2, as shown in FIG. 13(b).
In response to address change signal .phi..sub.1, equalize signal .phi..sub.E output through inverters 4 and 5 attain the H level as shown in FIG. 13(c). Therefore, precharging transistors 28 and 29 and equalizing transistor 30 receiving equalize signal .phi..sub.E at the gate electrodes are rendered conductive, respectively. Thus, as shown in FIG. 13(h) and (i), potentials BL.sub.1 and BL.sub.1 on bit line 10 and potentials BL.sub.2 and BL.sub.2 on bit line 11 are equalized to potential V.sub.CC -V.sub.th which is lower than power supply potential V.sub.CC by threshold voltage V.sub.th of respective precharging transistors 28 and 29.
On the other hand, row decoder 6 responds to address signal ADD changing from A.sub.2 to A.sub.1 at time t.sub.0 to cause potential WL.sub.2 on word line 7b to fall to the L level at time t.sub.1 and at the same time raises potential WL.sub.1 on word line 7a to the H level as shown in FIG. 13(d). In response to this, access transistors 18aa and 19aa in memory cell 9aa are rendered conductive.
At this time, potentials BL.sub.1 and BL.sub.1 on bit lines 10a and 11a, respectively, become equal by equalization as shown in FIG. 13(h); however, the potentials of drain electrodes of respective driver transistors 13aa and 14aa are held at the H level and the L level. The reason of this is a relatively large ON resistance of access transistors 18aa and 19aa.
In the meanwhile, column decoder 20 responds to address signal ADD changing from A.sub.2 to A.sub.1 at time t.sub.0 to cause potential CSL.sub.2 on column selection line 21b to fall to the L level at a time approximately the same time as time t.sub.1, as shown in FIG. 13(g). At the same time, column decoder 20 raises potential CSL.sub.1 on column selection line 21a to the H level as shown in FIG. 13(f).
In response to this, n channel MOS transistors 25a and 26a in I/O gating circuit 22 are rendered conductive, causing bit lines 10a and 11a to be connected respectively to I/O lines 23 and 24. Therefore, potentials IO and IO on I/O lines 23 and 24 are equalized as shown in FIG. 13(j).
Further, differential amplifier 31 is deactivated in response to equalize signal .phi..sub.E attaining the H level, whereby differential amplifier 31 outputs read data RD and RD, both of which attaining the L level, as shown in FIG. 13(k). Output buffer 32 outputs data D.sub.out of high impedance (Hi-Z), as shown in FIG. 13(m), in response to both of read data RD and RD attaining the L level.
As shown in FIG. 13(b), address change signal .phi..sub.1 output from the address change detecting circuit is fallen to the L level at time t.sub.2. In response to this address change signal .phi..sub.1, equalize signal .phi..sub.E output through inverters 4 and 5 is fallen to the L level as shown in FIG. 13(c).
In bit line equalizing circuit 27, precharging transistors 28, 29 and equalizing transistor 30 which receive the equalize signal .phi..sub.E are respectively rendered non-conductive. This stops equalization of bit lines 10 and 11, causing potentials at the H level and at the L level held in respective drain electrodes of driver transistors 13aa and 14aa in memory cell 9aa to be read respectively. Therefore, potentials BL.sub.1 and BL.sub.1 on bit lines 10a and 11a attain the H level and the L level, respectively, as shown in FIG. 13(h).
In response to this, a potential difference between potentials IO and IO on I/O lines 23 and 24 connected to bit lines 10a and 11a becomes greater, as shown in FIG. 13(j). The potential difference attains .DELTA.V.sub.1 at time t.sub.3 and increases to .DELTA.V.sub.2. As a result, potentials IO and IO attain the H level and the L level, respectively.
When the potential difference between potentials IO and IO attains .DELTA.V.sub.1, differential amplifier 31 receiving potentials IO and IO on I/O lines 23 and 24 outputs read data RD which rises to the H level and complementary read data RD at the L level, as shown in FIG. 13(k). Receiving these outputs, output buffer circuit 32 supplies externally output data D.sub.out which attains the H level to output pin 33, as shown in FIG. 13(m).
Then, as shown in FIG. 13(a), when externally applied address signal ADD changes from A.sub.1 to A.sub.2 at time t.sub.4, in response to this, internal address intADD output from address buffer 2 changes.
Address change detecting circuit 3 receiving the internal address intADD outputs address change signal .phi..sub.1 which attains the H level for a predetermined period until time t.sub.6, as shown in FIG. 13(b). In response to the address change signal .phi..sub.1, equalize signal .phi..sub.E output through inverters 4 and 5 attains the H level as shown in FIG. 13(c).
This causes precharging transistors 28 and 29 and equalizing transistors 30 which receive equalize signal .phi..sub.E at the gate electrodes to be rendered conductive. Therefore, as shown in FIG. 13(h) and (i), potentials BL.sub.1 and BL.sub.1 and BL.sub.2 and BL.sub.2 on bit lines 10 and 11 are equalized to potential V.sub.CC -V.sub.th which is lower than power supply potential V.sub.CC by threshold voltage V.sub.th of respective precharging transistors 28 and 29.
On the other hand, in response to address signal ADD changing from A.sub.1 to A.sub.2 at time t.sub.4, row decoder 6 causes potential WL.sub.1 on word line 7a to fall to the L level at time t.sub.5 as shown in FIG. 13(d), and at the same time raises potential WL.sub.2 on word line 7b to the H level as shown in FIG. 13(e). In response to this, access transistors 18bb and 19bb in memory cell 9bb are rendered conductive, respectively.
Also, in response to address signal ADD changing from A.sub.1 to A.sub.2 at time t.sub.4, column decoder 20 causes potential CSL.sub.1 on column selection line 21a to fall to the L level at approximately the same time as time t.sub.5 as shown in FIG. 13(f), and at the same time, raises potential CSL.sub.2 on column selection line 21b to the H level as shown in FIG. 13(g). In response to these potentials CSL.sub.1 and CSL.sub.2, n channel MOS transistors 25b and 26b in I/O gate circuit 22 are rendered conductive, respectively.
This connects bit lines 10b and 11b with I/O lines 23 and 24, respectively. Therefore, potentials IO and IO on I/O lines 23 and 24 are equalized as shown in FIG. 13(j).
Further, differential amplifier 31 is deactivated in response to equalize signal .phi..sub.E attaining the H level. As shown in FIG. 13(k), differential amplifier 31 outputs read data RD and RD, both of which attaining the L level. In response to both read data RD and RD attaining the L level, output buffer circuit 32 outputs data D.sub.out of high impedance (Hi-Z), as shown in FIG. 13(m).
Then, as shown in FIG. 13(b), address change signal .phi..sub.1 output from address change detecting circuit 3 is fallen to the L level at time t.sub.6. In response to address change signal .phi..sub.1, equalize signal .phi..sub.E output through inverters 4 and 5 is fallen to the L level, as shown in FIG. 13(c).
In bit line equalizing circuit 27, precharging transistors 28, 29 and equalizing transistor 30 which receive equalize signal .phi..sub.E are rendered non-conductive, respectively. This stops equalization of bit lines 10 and 11.
Accordingly, potentials at the L level and the H level held in respective drain electrodes of driver transistors 13bb and 14bb in memory cell 9bb are read to bit lines 10b and 11b. Therefore, potentials BL.sub.2 and BL.sub.2 on bit lines 10b and 11b attain the L level and the H level, respectively, as shown in FIG. 13(i).
In response to this, a potential difference between potentials IO and IO on I/O lines 23 and 24 connected to these bit lines 10b and 11b becomes greater. The potential difference attains .DELTA.V.sub.1 at time t.sub.7, and increases to .DELTA.V.sub.2. This causes potentials IO and IO to attain the L level and the H level, respectively.
When the potential difference between potentials IO and IO attains .DELTA.V.sub.1, differential amplifier 31 receiving potentials IO and IO on these I/O lines 23 and 24 outputs read data RD which rises to the H level and complementary read data RD which is at the L level, as shown in FIG. 13(k). In response to this, output buffer circuit 32 outputs data D.sub.out which attains the L level to output pin 33, as shown in FIG. 13(m).
Now, a problem associated with the above-described conventional semiconductor memory device will be described. In the conventional semiconductor memory device, differential amplifier 38 has already detected at the time when the potential difference between potentials IO and IO on I/O lines 23 and 24 increases to reach .DELTA.V.sub.1 (time t.sub.3 and t.sub.7) whether the data read to I/O lines 23 and 24 being at the H level or the L level. Then, differential amplifier 31 outputs read data RD and RD having the H level and the L level or having the L level and the H level depending on the detection.
Upon reception of read data RD and RD, output buffer 32 outputs data D.sub.out having the H level or the L level. It should be noted that equalization of bit lines is carried out for a predetermined time period (t.sub.0 -t.sub.2 and t.sub.4 -t.sub.6) after the change of externally applied address signal ADD. Therefore, even though differential amplifier 31 has already detected whether the data being at the H level or the L level, the potential difference between potentials IO and IO on I/O lines 23 and 24 continues increasing to reach the maximum value of .DELTA.V.sub.2.
Thus, a considerable time is required to render potentials IO and IO equal by equalization of I/O lines 23 and 24 after next time the address signal is changed into another address, thus requiring a long time before the subsequent data is read.